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Learning Verilog, RTL language

Verilog is a programming language specifically to program hardware at register transfer level. Digital logic consists of concurrent and sequential events.

Learn basics of Verilog coding.

Test your Verilog knowledge with examples

• Clock domain crossing
• Gray coding example

// Logic is to get Gray code from Binary code
function[5:0] binary2gray ;
input[5:0] value;
integer i;

begin
binary2gray[5] = value[5];
for (i=5; i>0; i = i - 1)
binary2gray[i-1] = value[i] ^ value[i - 1];
end
endfunction

• File read write operations
• Initial statements, conditional statements, synchronous counters,
• writing a test bench

RTL coding guidelines

1. Guideline 1:- Declare every possible state in conditional statements. Missing a declaration can result in un-intentional latches in design.
2. Guideline 2:- All the signals going across FPGA’s should be properly registered to avoid setup time violations.
3. Guideline 3:- All the IO’s should be properly constrained during synthesis or layout to avoid setup or hold time violations.
4. Guideline 4:- Implementing clock domain crossing is the most complicated design scenario in digital circuits. Necessary steps to design involves detailed analysis of the clocks across the domain.Following are some ideas to implement clock domain crossing: Use rate – change FIFO, Double clocking,Gray encoders for counters.
5. Guideline 5:- Wires and Registers should be correctly implemented in Verilog. Registers must be used within always blocks. Wires are used for connectivity outside always blocks and are generally used with assign statements or for connectivity not requiring any registered delay.
6. Guideline 6:- Blocking vs. non-blocking statements. Blocking statements are always used within combinatory block to execute statements in a sequence. Non – blocking statements are always executed in a sequential logic block to execute all statements in at either clock edge.
7. Guideline 7:- Never mix blocking and non-blocking statements in a single always block in Verilog.
8. Guideline 8:- Suggested approach to write synthesizable RTL is to separate the synchronous and combinational logic into separate processes (always blocks in Verilog).
9. Guideline 9:- After simulating the design, always synthesize it and check for latches, unbounded component, tri-state logic etc.
10. Guideline 10: - Conditional IF statements should not be used in parallel states. Case statements best